Guidelines for Logic Synthesis

The guidelines suggested here are not hard and fast rules for effective synthesis. 

These are applicable in most cases and exceptions to these guidelines are possible. 

For better results from synthesis, specify accurate point to point delays for asynchronous paths. Use the create.clock and group path commands to constrain synchronous paths in the design. In general, the synthesis tool is tailored towards path optimization. Hence, it responds better to a greater detail of constraints. 

Separate negative and positive edge flip-flops into separate hierarchical blocks. In other words, avoid having both kinds of flops in the same hierarchical module. This makes the debug process and timing analysis during synthesis much simpler. Moreover, this can help simplify test insertion. 

Group finite state machines and optimize them separately. State machine extraction and optimization process is more effective when the fsm is isolated. The group -fsm command can be used to achieve this. 

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