Flip flop falling edge

The assignment to output Zee occurs only at the falling edge of the clock. Variable Zee is inferred to be a falling-edge-triggered flip-flop. The flip-flop shown in the figure has a data-select, that is, the input Control selects either A or B as the data for the flip-flop. 

Figure 2-47 Falling-edge-triggered flip-flops inferred.

The variable Counter is assigned under the control of a falling edge of clock ClockB. Thus, two falling-edge-triggered flip-flops are synthesized for Counter. 

If a falling-edge-triggered flip-flop are to be inferred, then the clock edge event posedge Clk needs to be replaced by ... 

In this case, falling-edge-triggered flip-flops are inferred for variable Temp, in addition to those for NextState. 

Since NextState is assigned a value under the control of a clock edge (Stmt C) and it is also assigned asynchronously (Stmt A and B), a falling-edge-triggered flip-flop with asynchronous preset and clear is synthesized. This is shown in Figure 2-53. Note that four flip-flops are required. The first flip-flop (the leftmost bit of NextState) has both asynchronous preset and clear terminals since it needs to be preset on Reset and cleared on Set. Similarly, the fourth flip-flop has both asynchronous preset and clear terminals since it needs to be preset on Set and cleared on Reset. The... 

A single dock signal cannot drive bodi rising and falling edge flip flops within the same architecture. 

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