Fixing Min Delay Violations

Once the max delay requirements imposed due to the setup constraints for the sequential cells have been met, DC can be used to fix the minimum path delay requirements. Since the path delays are the maximum in the worst case timing analysis or worst case operating conditions, max delay requirements must be met in the worst case operating conditions. 

The minimum delay requirements are set by the hold constraints for the sequential cells. Hold time problems are caused due to short delay paths between registers which cause the data signal to propagate through two adjacent flip-flops on a single clock edge. Since path delays are the shortest under best-case operating conditions, hold time problems are maximum in these conditions. Hence, hold violations have to be fixed under these conditions. 

Hold time problems will generally occur in shift register structures or scan chains. Since by default DC treats the clock as ideal with no path delays, one must account for the network delay by using the set clock skew -propagated command. 

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