Fault tree analysis logic gates

Fault Tree Analysis Faiilt tree analysis permits the hazardous incident (called the top event) frequency to be estimated from a logic model of the failure mechanisms of a system. The top event is traced downward to more basic failures using logic gates to determine its causes and hkelihood. The model is based on the combinations of fail-... 

Fault Tree Analysis (FTA) is a well known and widely used safety tool, implementing a deductive, top down approach. It starts with a top level hazard, which has to be known in advance and "works the way down" through all causal factors of this hazard, combined with Boolean Logic (mainly AND and OR gates). It can consider hardware, software and human errors and identifies both single and multiple points of failure. Both a quantitative and qualitative analysis is possible. 

Logic Gate As pertains to fault tree analysis (FTA) and/or the Management Oversight and Risk Tree (MORT), a symbol used to idenhly the association between events on a logic tree. 

Fault tree analysis (FTA) provides a logical representation of many events and component failures that may combine to cause one critical event (e.g., pipeline explosion). It uses logic gates to show how basic events may combine to cause the critical top event. The top event would normally be a major hazard such as "pipeline SCC" as in the example shown in Fig. 12.10. The most commonly used tree symbols and gates used in the construction of fault trees are illustrated in Fig. 12.11 and briefly described here [12] ... 

CONSTRUCTING THE FAULT TREE. Fault tree construction begins at the top event and proceeds, level by level, until all fault events have been traced to their basic contributing events or basic events. The analysis starts with a review of system requirements, function, design, environment, and other factors to determine the conditions, events, and failures that could contribute to an occurrence of the undesired top event. The top event is then defined in terms of sub-top events, i.e., events that describe the specific "whens and wheres" of the hazard in the top event. Next, the analysts examine the sub-top events and determine the immediate, necessary, and sufficient causes that result in each of these events. Normally, these are not basic causes, but are intermediate faults that require further development. For each intermediate fault, the causes are determined and shown on the fault tree with the appropriate logic gate. The analysts follow this process until all intermediate faults have... 

Then one must apply Boolean algebra to each logic gate to determine the probability of each intermediate event. Ultimately, the analysis calculates the probability for the top event. Example 36-1 illustrates the fundamentals of this process for the fault tree shown in Figure 36-5. 

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