Fabrication of the a-Si H FET

Two important points were established at an early stage of the present development. The first is that conventional photolithographic techniques, widely used in the semiconductor industry, can be applied successfully to a-Si H thin-film devices. The second equally relevant point is that the a-Si H FETs perform adequately at voltages below 15 V, so that they are compatible with modern integrated-circuit vol tage levels. 

The unwanted Si is etched away and contact holes, denoted by A in Fig. 3, are etched through the silicon for connecting the drain contact to the ITO pads. The top electrode configuration, S and D, is then formed from the 

The n+ underlay was used with the source and drain contacts to provide good electron-injecting properties. This caused the reproducibility of the contacts to increase, and the ON current obtained in this way increased significantly. For example, devices with n+ contacts consistently produced source-drain currents a factor of about three higher than the best currents obtained without the n+ layers. 

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