Data path synthesis

N. Wehn, M. Held, and M. Glesner. A novel scheduling/allocation approach for data-path synthesis based on genetic paradigms. Proc. IFIP Working Conference on Logic and Architecture Synthesis, Paris, Prance, May 1990. 

C. Y. Hitchcock and D. E. Thomas. A method of automatic data-path synthesis. Proc. 20th DAC paper 31.3, 1983. 

The last criterion applied to select systems for inclusion was timeliness. We reduced this criterion to a single number with a few exceptions of historical value, no systems without publications after 1985 were included. Since 1985, sessions with titles such as Synthesis of Logic Structures from Behavioral Descriptions , Control/Data Path Synthesis , High-Level Synthesis , etc., have become numerous in m jor conferences, leading to our choice of that cut-off date. 

Allocation, which assigns each operation to a piece of hardware. Allocation involves both the selection of the type and quantity of hardware modules from a library (often called module assignment) and the mapping of each operation to the selected hardware. Allocation is sometimes called data path synthesis or data path allocation. 

M. Balakrishnan, A.K. Majumdar, D.K. Banerji, and J.G. Linders, Allocation of Multi-Port Memories in Data Path Synthesis, IEEE Transactions on Computer-Aided Design, vol. 

C.Y. Hitchcock III and D.E. Thomas, A Method of Automated Data Path Synthesis, Proceedings 20th Design Automation Conference, pp. 484-489, June 1983. 

J. Lee, Y. Hsu, and Y. Lin, A New Integer Linear Programming Formulation for the Scheduling Problem in Data-Path Synthesis, ICCAD 89, Santa Clara, CA, November 1989. 

P.G. Paulin and J.P. Knight, Force-Directed Scheduling in Automatic Data Path Synthesis, Proceedings 24th Design Automation Conference, pp. 195-202, Miami Beach, Florida, June 1987. 

Partitioning and scheduling using BUD, data path synthesis using DAA, and a signal processor example. 

Overview of the project, including scheduling and data path synthesis, module binding, controller allocation, floorplanning, and layout. 

Knowledge acquisition, data path synthesis, the MCS6502, and the IBM System/370. 

Data path synthesis phases, and a PDP-8 code fragment example. 

AT T s CHARM (C,oncurreiit Hardware Allocation by fiepeated Merging) system uses AT T s Bridge system for scheduling. CHARM (previously called SAM) then performs the data path synthesis. See also AT Ts Bridge System. 

Nam-Sung Woo, A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System , Proc. of the 27th DAC, pages 505-510, Jiuie 1990. 

Data path synthesis, including register allocation and binding, and three code segment examples. 

Hyunchul Shin and Nam S. Woo, A Cost Function Based Optimization Technique for Scheduling in Data Path Synthesis , Proc. ofICCD 89, pages 424-427, October 1989. 

The HAL (Hardware Allocator ) system was Paulin s thesis work at Carleton University. HAL includes scheduling, data path synthesis, and design iteration. 

Other synfhesis systems, scheduling and data path synthesis, design iteration, a second-order differential equation example, MAHA s example (originally from Park), a pipelined 16-point digital FIR filter example, Tseng s running example, and a fifth-order digital elliptic wave filter example. 

Scheduling and data path synthesis, a second-order differential equation example, and Tseng s running example. 

Scheduling, Data Path Synthesis, Controller Design, and Module Binding... 

A formal Register-Transfer level hardware model, and automatic data path synthesis using linear programming techniques. 

D.E. Thomas, C.Y. Hitchcock III, T.J. Kowalski, J.V. Rajan, and R.A. Walker, Methods of Automatic Data Path Synthesis , IEEE Computer, pages 59-70, December 1983. 

System overview, transformations, scheduling, data path synthesis using EMUCS and DAA, multilevel representation, andtheMCS6502. 

Charles Y. Hitchcock III, A Method of Automatic Data Path Synthesis, Master s Thesis, Dept, of Electrical and Computer Engineering, Carnegie Mellon University, January 1983. 

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