D re-design of PipeRench see colour plate

All the pads are placed on the bottom level chip. Since the bottom chip has a smaller footprint than the original design does, the distance between pads is uniformly scaled down so that the pads can be fitted to the short perimeter. 

In the original monolithic design, the reconfigurable fabric is surrounded by a 

In the new design, we use two H-trees to deliver clock signals for the top level chip and bottom level chip, respectively. The two H-trees are interconnected through 128 inter-chip contacts to reduce clock skew. 

Finally, we need 900 inter-chip contacts for power distribution so make sure (1) current density of a 1-micron thick A1 power wire should be within 0.4 mA/ micron to 1 mA/micron[13] (2) current density of an inter-chip contact should be under 0.1 mA/micron[13]. According to our calculation, the worst-case IR dropping is within 9.6 mV. 

In the 2.5-D layout, the bottom chip has a surface area of 3.9 mm by 7.8 mm. If we assume the area pitch of inter-chip contact is 5 pmx 5 pm, we can have up to 1.2 million inter-chip contacts on the chip surface. Since the 2.5-D re-design is done manually, the actual number of used inter-chip contacts is far less than the above available number. 

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