Configurable Logic Blocks CLBs

Example 7.1 shows a VHDL and Verilog code template that can be used to infer flops with clock enables. The flops available in CLBs already have a clock enable pin, hence, one can use the code template in Example 7-1 for design scenarios that need gated clocks. The intent is to exploit all the dedicated logic resources available rather than use the limited combinational resources to implement the gated clock logic. 

Example 7.1 Inferring Flip-Flops with Clock Enable 

Xilinx XC4000 devices can efficiently implement RAMs and ROMs using CLB function generators. XC4000 libraries include 16x1 and 32x1 RAM and ROM primitives that you can instantiate in your code. These primitives must be instantiated in your HDL code to efficiently implement memory in the XC4000 family. In the 

Synopsys environment, these primitives are black boxes and will remain as unresolved references. The Xilinx SYN2XNF program automatically merges the XNF file for the memoiy when translating the Synopsys generated XNF file to Xilinx XNF format as described in section 7.2.2. 

The following are the different variables that must be specified to synthesize a design using Xilinx technology libraries. 

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The configuration memoiy of the used drtex 5 is divided into frames. Each frame contains 41 words of 32 bits each, for a total of 1312 bits. Frames are accessed by their individual addresses, through the Frame Address Register (FAR), and are divided into block type, top/bottom bit, row, major address and minor address. Each frame row comprises several rows of the basic FPGA components, such 20 rows of Configurable Logic Blocks (CLBs) and four block RAMs. 

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