Combinational logic coalescing

A disadvantage of this approach is that the complexity of the algorithm is related to the number of branches and nesting depth of the conditionals. Therefore, the hardware modeling style has a large impact on the execution time of the algorithm. 

An expression block defines the largest scope (without crossing control step boundaries) in which combinational logic synthesis can be applied. There are two advantages in performing coalescing  

An example of coalescing is given below. Originally, the specification consist-s of a set of Boolean operations and two I/O statements, grouped in a data-parallel statement block, i.e. operations can execute in parallel subject to data-dependencies. 

Coalescing produces two expression blocks, one before the VO statements and one after. 

Combinational coalescing is implemented by clustering the BIF based on data-flow dependencies. Logic operations are gathered into a cluster subject to the restriction that no sequential operations exist that both reference the outputs of operations in the cluster and produce outputs that are referenced by operations in the cluster. The algorithm is straightforward and is not described here. 

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Many of the above transformations are weU-documented in texts on compiler design. The reference stack and combinational logic coalescing techniques are new. They are described in the next two sections. 

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