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Polysilicon buried

Next, the sacrificial layer is deposited as a TEOS (Tetraethylorthosilane) oxide about 1.5 pm thick and is coated with photoresist, patterned and etched to form contact openings to the buried polysilicon layer (Fig. 5.3.11b). [Pg.116]

LPCVtJ deposition of buried polysilicon Doping of buried polysilicon... [Pg.117]

Figure 8.14 Cross section of a single deformable mirror pixel using a buried polysilicon wiring layer to address the actuator electrode. (Used with permission from S.A. Cornelissen, P.A. Bierden, and T.G. Bifano, Development of a 4096 element MEMS continuous membrane deformable mirror for high contrast astronomical imaging, Proc. SPIE 6306, p. 630606-1 [2006].)... Figure 8.14 Cross section of a single deformable mirror pixel using a buried polysilicon wiring layer to address the actuator electrode. (Used with permission from S.A. Cornelissen, P.A. Bierden, and T.G. Bifano, Development of a 4096 element MEMS continuous membrane deformable mirror for high contrast astronomical imaging, Proc. SPIE 6306, p. 630606-1 [2006].)...
Figure 15. Photovoltaic detector potential well. The example in this figure is the p-n junction of a n-channel CCD. The x-y-z axes match the orientation shown in Fig. 5. The charge generated in the 3-D volume of a pixel is swept toward a 2-D layer, which is the buried channel that is 0.25-0.5 pm from the front surface of the detector. The z-direction potential is created by the p-n junction combined with the voltages on the polysilicon wires deposited on the frontside of the CCD (not shown in this figure). Figure 15. Photovoltaic detector potential well. The example in this figure is the p-n junction of a n-channel CCD. The x-y-z axes match the orientation shown in Fig. 5. The charge generated in the 3-D volume of a pixel is swept toward a 2-D layer, which is the buried channel that is 0.25-0.5 pm from the front surface of the detector. The z-direction potential is created by the p-n junction combined with the voltages on the polysilicon wires deposited on the frontside of the CCD (not shown in this figure).
FIGURE 3.50 Side view of an EWOD device (not to scale). The bottom plate served as the base for a pattern of polysilicon EWOD electrodes (1 mm2, 4-pm gap) buried under the thermal oxide. A top plate was formed from ITO on glass both plates were coated with Teflon-AF. The plates were joined with double-sided adhesive tape as a spacer [518], Reprinted with permission from the American Chemical Society. [Pg.100]

Another type of integrated micromachined structure different from the anchored polysilicon surface films occurs by adding the micromachined structure to the wafer after the IC is created by plating or film deposition. Texas Instruments DLP technology with aluminum metal is the most well known example [3]. However, these types of structures are not used in large-scale automotive production. Another class of micromachined devices is made from silicon-on-insulator (SOI) components and could easily be described as surface micromachined, since they have mechanical structures on the surface. These devices use the buried oxide of the bonded wafer as the sacrificial layer [6]. A similar structure created by epitaxial deposition of silicon over oxide produces a polysilicon structure [7]. Figure... [Pg.95]


See other pages where Polysilicon buried is mentioned: [Pg.116]    [Pg.117]    [Pg.117]    [Pg.118]    [Pg.116]    [Pg.117]    [Pg.117]    [Pg.118]    [Pg.306]    [Pg.90]    [Pg.2779]    [Pg.3005]    [Pg.14]    [Pg.263]   
See also in sourсe #XX -- [ Pg.116 ]




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Buried

Burying

POLYSILICONE

Polysilicon

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