Architecture highly multiplexed

The data/control-flow graphs are large and complex. Moreover, the applications require clock frequencies of 10 20 MHz, whereas the intermediate data throughput and sample frequencies remain far below 1 MHz. As a result of these factors, the hardware-sharing factor (HSF) is much larger than 1, resulting in highly multiplexed architectures. 

The highly multiplexed data-path architecture supports mapping of computationally intensive algorithms with a large hardware sharing factor. 

Novel design methodologies and synthesis techniques for multiplexed processor architectures intended for irregular high- and medium-throughput applications. Both control-flow- and data-flow-dominated target domains are treated. 

A second important architecture style for real-time signal processing systems is the multiplexed processor style, characterized by a set of application-specific, time-multiplexed data-paths steered by a hierarchically organized controller. This style is tuned to irregular applications, requiring a medium to high sample rate (10 kHz - 10 MHz). Many applications at these rates require a combination of computation-intensive arithmetic and complex decision-making operations. For these applications, the array style (as described in section 5) is unsuitable. 

Placing the ADC in front of the output, downstream of the column multiplexer, requires a very high-speed convertor. The required conversion rate for an array with a single high speed ADC can exceed SOM to lOOM conversion per second per output. Most implementations of this architecture employ several ADCs along the bottom of the ROIC in order to manage the overall conversion rate. The types of... 

---