An UART Model

When synthesized, flip-flops are inferred for InLatch, Result, Exponent and Done. 

The first block DIV is a frequency divider. This block has 2 modes of operation, the normal mode and the test mode. In the test mode, the UART chip runs 16 times faster than in the normal mode. Also, the transmission data rate of the UART chip is 16 times faster than the receiving rate. Each block is initialized by setting the reset line low by applying a 0 to port MR. The TX block accepts 8-bit parallel data from the microprocessor interface (MP) block and transmits it serially to the RS-232 port through port DOUT. Conversely, the RX block receives serial data input, and sends it in 8-bit parallel format to the MP block. Again, the transmitter runs at 16 times the speed of the receiver. The microprocessor interface (MP) block asynchronously controls the parallel data flow between the RX / TX blocks and the microprocessor data bus. 

The UART top-level model glues all these blocks together using module instantiations. The microprocessor entity, MP, is described in the structural style, that is, using module instances. The remaining three are described using the behavioral style. In this chapter, only the behavioral blocks are described. 

Here is the behavioral model for the transmitter block TX. This model is a synthesizable model. Rising-edge-triggered flip-flops are inferred for variables TBR, TR, TRE, TBRE, DOUT, CBTT and PA this is because these variables are assigned values under the control of clock CK. 

Here is the behavioral model for the receiver block RX. This model is also synthesizable. Flip-flops are inferred for variables START, CBIT, CSAM, DI, PI, SR, DR, DOUT, PERR, FERR and OERR. 

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