Wafer level layout

FIGURE 15.15 (a) Layout of dice and profilometry scans over a 200-mm wafer for wafer-level height distribution study, (b) Wafer-level height distribution for CMP over a nonideal die layout (four of the ten scan lines have been removed for clarity) (from Ref 114). 

Design and model the sensor function on the basis of a comprehensive set of model parameters (i.e., geometrical dimensions and material properties) and calculate tolerance bands for all layout-specific model parameters (including those for wafer-level packages) so that functional specs are safely met (see Section 4.1). 

The ILD thickness variation sources can be categorized into wafer-level, die-level, die and wafer interaction, and residual terms. The wafer-level variation is often caused by process perturbation and drifts in equipment and consumables, and is relatively invariant of pattern density and other layout effects. On the other hand, the die-level variation is attributed to... 

Micro/nanostructures generated using these and related top-down approaches are geometrically and electrically homogeneous, with layouts that can be controlled over a wide range to realize not only ribbons and wires but also bars, platelets, membranes, and other structures. The main limitations of the top-down approach are as follows (1) The composition of the fabricated objects is limited to materials that are readily available in wafer or thin-film forms, (2) the etching processes can lead to some level of roughness on the surfaces of the structures, and (3) dimensions of less than 20 nm, for other than the thickness, are difficult to obtain reliably. 

Budding on the general wafer removal models of the previous section, this section considers models related to how wafer surface material is planarized. These include models for feature-level evolution, and die-level models for planarization as functions of layout, pad, and asperity properties. Again, our goal is not to provide a comprehensive survey of existing CMP models instead, our purpose is to present models that demonstrate how key physical effects in planarization can be predicted. 

Modeling of the CMP process. To calculate the wafer topography evolution during the CMP process, PD p(x, y) needs to he extracted from the chip layout. With initial values of up area thickness and step height, the die-level pressure distrihution p x, y) can he obtained hy solving Eqn (6.27). Once p x, y) is solved, pu(x, y) and pi x, y) can he calculated hy Eqn (6.26). Then we utilize Preston s equation with local pressures pu(x, y) and pd(x, y) to calculate the instantaneous MRR of up area and down area as... 

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