UMOSFET

However, after the first years of great expectations supported by early impressive results reported by Palmour et al. in 1994 [5], it became clear that initial predictions of a revolutionary improvement in power switching by employing vertical SiC MOSFETs are difficult to accomplish due to multiple reasons. In particular, a critical analysis of performance advantages and limitations of 4H-SiC power UMOSFET structure has been made by Agarwal et al. in 1996 [6]. The main issues raised in this work were ... 

Figure 5.1 Schematic cross section of a classical UMOSFET.

Figure 5.2 Comparison of the practical minimum for a specific drift region on-resistance of 4H-SiC UMOSFET with thermal SiOj gate dielectric to the theoretical values calculated for 4EI-SiC and Si as a function of blocking voltage. Caughey-Thomas mobility parameters for Si used in this calculation are taken from [12].

Two-dimensional numerical simulations of a 1.2-kV 4H-SiC UMOSFET with a 600-A layer of HfO as gate dielectric confirmed the benefits of using high-k gate dielectric in SiC UMOS transistors. Figure 5.3 shows electric field distribution in... 

So far there has been no published data on inversion channel mobility in metal-HfO -SiC structures. However, even assuming extremely poor channel mobility of 0.1 cmV(V s), HfO -SiC UMOSFET can offer total specific on-resistance equal to... 

Figure 5.4 Comparison of Ron sp classical structure 4H-SIC UMOSFET with different gate dielectrics and channel mobilities.

One of the most important issues preventing commercialization of power SiC MOSFETs so far is MOS channel resistance that results from the extremely low inversion channel mobility in 4H-SiC [19]. This problem may become especially significant in the case of 4H-SiC UMOSFETs, where the oxide-semiconductor interface is severely damaged by plasma etch when the trenches are formed. In general, there are two major approaches to minimize the channel component of on-resistance ... 

As previously discussed, silicon dioxide appeared to be a nonideal gate dielectric to be used with silicon carbide in UMOS configuration. Different design solutions used to protect SiO gate dielectric from a high electric field in SiC UMOSFETs resulted in dramatically complicated transistor structure. Because of the problems with SiC UMOSFET, the classical vertical double-diffused MOSEET (VDMOS)... 

Figure 5.6 Schematic cross-section of an improved high-voltage 4H-SiC accumulation mode UMOSFET. (From [25], 1998 IEEE. Reprinted with permission.)...

Agarwal, A. K., et ah, A Critical Look at the Performance Advantages and Limitations of 4H-SiC Power UMOSFET Structures, Proc. of 8th Inti. Symposium on Power Semiconductor Devices and ICs, May 23, 1996, pp.119-122. 

Sugawara, Y., and K. Asano, 1.4 kV 4H-SiC UMOSFET with Low Specific On-Resistance, Proc. of the 10th Inti. Symposium on Power Semiconductor Devices and ICs, ISPSD 98, June 3-6, 1998, pp. 119-122. 

Figure 8 The power UMOSFET structure and the electric field profile in the blocking state.

Figure 9 Current flow path in the UMOSFET in the on state with the primary resistances in the current flow path between source and drain.

Figure 10 Impact of inversion layer mobility on the specific on-resistance of a 1000-V SiC UMOSFET. The percentage contributed by the channel resistance can be read from the right-hand side.

Figure 11 Impact of inversion layer mobility on the specific on-resistance of SiC UMOSFETs with...

Because of the problems with SiC UMOSFETs pointed out in the previous section, it becomes important to consider alternative device embodiments. Two device structures described in this section make it possible to circumvent these issues. 

M Bhatnagar, D Alok, BJ Baliga. SiC Power UMOSFET Design, Analysis, and Technological Feasibility. Proceedings 5th Conference on Silicon Carbide and Related Materials, 1993, p 703. 

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