Transputer architecture

Parallel processing of information is a technique that speeds computer operations without the need to push the limits of existing technology by attempting to build increasingly faster processors. A typical outline of transputer architecture compared with that of a standard computer is shown m Figure 43.3. 

A typical transputer architecture. The transputer (sometimes referred to as a computer on a chip) has four input/output links (0, 1, 2, 3) to other transputers, a channel for inputting/requesting data (event link), some built-in random-access memory, an interface to the main operating system (clock, boot, etc.), and an external memory interface. Internal communication is via a bus. 

Transputers. At higher levels of coimectedness there is a wide variety of parallel computers. A great many parallel computers have been built using INMOS Transputer chips. Individual Transputer chips mn at 2 MELOPS or greater. Transputer chips have four communication channels, so the chips can readily be intercoimected into a two-dimensional mesh network or into any other interconnection scheme where individual nodes are four-coimected. Most Transputer systems have been built as additions to existing host computers and are SIMD type. Each Transputer has a relatively small local memory as well as access to the host s memory through the interconnection network. Not surprisingly, problems that best utilize local memory tend to achieve better performance than those that make more frequent accesses to host memory. Systems that access fast local memory and slower shared memory are often referred to as NUMA, nonuniform memory access, architecture. 

Peter Willett s paper elsewhere in this book refers to some developments in novel architectures transputers and clusters of processors such as the Intel iPSC. 

Transputer n. A type of process-control architecture in which computing elements are linked not only by a systems bus but also by additional links combining software and hardware, called firmware links. The gain in speed of handling control tasks (as of 11/91) is about a factor of 20, permitting the use of complex control algorithms for, say, injection molding, that could not be used with conventional microprocessor/bus systems. 

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