Synthesis modeling style

Because of these problems, different synthesis systems support different Verilog HDL subsets for synthesis. Since there is no single object in Verilog HDL that means a latch or a flip-flop, each synthesis system may provide different mechanisms to model a flip-flop or a latch. Each synthesis system therefore defines its own subset of Verilog HDL including its own modeling style. 

This limitation creates a severe handicap because now the designer not only has to understand Verilog HDL, but also has to understand the synthesis-specific modeling style before a synthesizable model can be written. The typical design process shown in Figure 1-4 can not always be followed for Verilog HDL synthesis. 

Yamagishi, J., Onishi, K., Masuko, T., and Kobayashi, T. Modeling of various speaking styles and emotions for hmm-based speech synthesis. In Proceedings of Eurospeech 2003 (2003). 

Using description models and style that do not match requires complicated model analysis and sophisticated style-transformation techniques. Thus, extension of synthesis to system levels requires a matching of models, abstractions, and design styles. 

The second approach is to use a standard simulation language such as VHDL for synthesis. Such a language is, however, burdened by constructs necessary for simulation and not for synthesis. Furthermore, simulation models are not adequate for many design styles. 

A structural style architecture can be used to model sequential circuits. The storage elements used in a sequential circuit are edge-triggered latches - flip flops - or level-triggered latches - transparent latches. These can be instantiated from libraries provided by the synthesis tool or technology vendor. This can limit the flexibility of an implementation as not all vendor technologies will support all types of storage elements. Elements such as flip flops with asynchronous preset and clear inputs, for example, may be omitted from a library. 

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