SPICE simulation on the critical path

Lumped Capacitance of inter-chip contact (fF) Bus Wire Delay (ns) Critical Path Delay (ns) Clock Frequency (MHz) Improvement to 2D Solution 

From the design experience of 2.5-D PipeRench, we found that substantial performance gain can be achieved because the 2.5-D integration style provides significant flexibility to cut down long wires through the usage of inter-chip contacts. 

In Chapter 1, we discussed the performance gap between microprocessors and DRAM based main memory. The so-called memory wall affects microprocessor performance in two aspects bandwidth and latency. Latency is the waiting time after a memory request is sent to the memory controller, while bandwidth is the maximum throughput a memory system could provide. 

Compared with bandwidth, memory latency is improved at an even slower pace. The classical way to hide the excessive latency is to place frequently used 

General Out-of-order microprocessor with Alpha instruction set 

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