Silicon area of the MCM implementation

Based on the above analysis, the silicon areas of the MCM implementation for different numbers of dies can be computed and shown in Fig. 2.4. 

Finally, we pick up the cost optimum of each VLSI integration schemes discussed above and compare them in Fig. 2.5. To make a clearer comparison, we normalize the costs of different integration styles to that of the monolithic System-on-chip. 

In Fig. 2.5, the Vertical-axis is the normalized silicon area consumed to fabricate a working system, while the Horizontal-axis is the defect coverage level of each system component or device level. 

Mulliple-Dies on One Wafer 2,5-D (4 Slices) MCM (3 dies wilh 

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