Shared wafer processes

One factor that is different from earlier transitions is the increased reliance IC manufacturers are placing on the capital equipment vendors to share some of the burden of the development costs associated with the transition to 300-mm wafers. Although this shift is complementary to the maturing capabilities of the equipment vendors, it is placing enormous strain on them. Few vendors are in a position to provide new tools, engineering support, and process support in multiple sites for upward of a year with only the promise of remaining in contention for the substantial capital equipment purchases that can justify such significant investment of resources. 

Chemical vapor deposition and heterogeneous catalysis share many kinetic and transport features, but CVD reactor design lags the corresponding catalytic reactor analysis both in level of sophistication and in scope. In the following we review the state of CVD reactor modelling and demonstrate how catalytic reactor design concepts may be applied to CVD processes. This is illustrated with an example where fixed bed reactor concepts are used to describe a commercial "multiple-wafers-in-tube" low pressure CVD reactor. 

The most commonly implemented and extensively investigated CMP steps are the preparation of planar premetal dielectrics (PMD) and interlayer dielectrics (ILD) films on wafer. Together they are labeled as oxide CMP, as they both use the same materials that are based on silicon dioxide. Both processes share the integration concerns in deposition, planarity, and defectivity. 

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