Roll-up Active-matrix Backplane Design

(1) and (2) of Chapter 13 of this book are used. The field-effect mobility is 0.010 cm2 V-1 s 1 (linear mobility extracted from the transfer characteristics for Vgs = —20 V and Vds = —1 V), and the leakage current is a few picoamps. 

The display contains 240 rows and 320 columns. The pixel size is 300 x 300 pm2 resulting in a display diagonal of 4.7 inches. An overview of the display design is shown in Fig. 14.5. All contacts to the display are situated on the left. The row electrodes are arranged horizontally and the column electrodes are arranged vertically. The three small blue rectangles are the contacts to the common electrode. 

A field shielded pixel structure is used. The cross-section of the active-matrix stack is shown in Fig. 14.6. The first four layers, defining the TFT, are identical with the stack presented in Section 14.2. The rows of the display are processed on the first metal level whereas the columns are processed on the second metal level. In the field-shielded pixel design, the pixel electrode is defined in a third metal level of gold, resulting in a six-mask process. The pixel pad overlaps the storage capacitor, TFT, and column lines with a 6 pm thick polyvinylphenol layer acting as inter-layer dielectric. The optical aperture thereby increases to over 95%. The TFT channel length (L) and width (W) are 5 pm and 140 pm, respectively. 

To estimate the transistor requirements for our display, we make use of a transistor model (Detcheverry 2000) that includes a gate-voltage-dependent field-effect mobility  

The required field-effect mobility for our display can be determined by performing circuit simulations with the circuit shown in Fig. 14.7. The term ju0 in Eq. (1) is 

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