Porous Silicon-Based Electronic Devices

The material properties of PS offer new ways of making electronic devices. For the manufacture of cold cathodes, for example, oxidized microporous polysilicon has been found to be a promising material. The application of basic semiconductor processing steps such as doping, oxidation and CVD to a macroporous material enable us to fabricate silicon-based capacitors of high specific capacitance. Both devices will be discussed below. 

In many electronic applications, e.g. vacuum tubes, an electron emitting cathode is an indispensable part of the device. For many such devices cold electron emission is favorable because of its lower energy consumption. 

A schematic view of the cold cathode fabrication process is shown in Fig. 10.18. The cold cathode is fabricated by low pressure chemical vapor deposition (LPCVD) of 1.5 pm of non-doped polysilicon on a silicon wafer or a metallized glass substrate. The topmost micrometer of polysilicon is then anodized (10 mA cnT2, 30 s) in ethanoic HF under illumination. This results in a porous layer with inclusions of larger silicon crystallites, due to faster pore formation along grain boundaries. After anodization the porous layer is oxidized (700 °C, 60 min) and a semi-transparent (10 nm) gold film is deposited as a top electrode. 

A macroporous silicon substrate with pores of about a micrometer and a pore depth of a few tenths of a millimeter offers a surface area enhancement of about two or three orders of magnitude compared to an unetched silicon surface. An example of such a macroporous substrate used for fabrication of a silicon capacitor (SIKO) is shown in Fig. 10.20 b. 

The electrical characteristics of the SIKO are summarized below. The specific capacitance of the device shown in Fig. 10.20 is close to 4 pFV mnT3, and with smaller designs values of up to 20 pFV mnT3 are feasible. The range of manufacturable capacitance is not only a question of chip size but also of defect density of the ONO. Surprisingly, a defect density of l(T3cnT2 has been observed for the porous structure, which is much smaller than the defect density of planar ONO layers, which is in the order of 0.1 cnT2. This low defect density can be understood if the defect density of planar films is assumed to be due to particles that do not penetrate into the pores. 

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This chapter summarizes the main theoretical approaches to model the porous silicon electronic band structure, comparing effective mass theory, semiempirical, and first-principles methods. In order to model its complex porous morphology, supercell, nanowire, and nanocrystal approaches are widely used. In particular, calculations of strain, doping, and surface chemistry effects on the band structure are discussed. Finally, the combined use of ab initio and tight-binding approaches to predict the band structure and properties of electronic devices based on porous silicon is put forward. 

Ohmic and rectifying contacts to porous silicon are important and challenging for the commercial applications of PS-based electronic, optoelectronic, and sensor devices. The choice of contact materials and the nature of PS surface (including porosity) are the prime factors for the successful achievement in the contact formation with the desired specific contact resistance. Surface modification of porous silicon by Pd improves both ohmic and rectifying contacts along with the stability as it was verified by intermittent I-V studies. Verification of specific contact resistance at regular intervals can be an alternative method to study the junction stability. 

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