Operand length

The key idea in this work is to get the upper (temporarily unused) bits of an adder to work. In this point our effort fundamentally differs from techniques to speed up the addition itself, as we leave the addition principle untouched. The first thoughts in this section handle a general case, where we do not know the actual length of the operands. Thus, we have to determine the last position a carry propagates to. 

VHDL defines logical operators for the basic types of BIT and BOOLEAN or any one-dimensional array of either type, such as BIT VECTOR. The result generated by each operator is of the same type and has the same length as the operands supplied. Hence, the operands must be identical in type and length to allow each matching element to be compared. The synthesizer should detect any errors of this t)rpe, but they may go undetected until run time when simulating the description. The operators are listed in Table 4.1. 

Z<=W and X operands match each other in length but not the target... 

The operands must be of the same type but may vary in length. Examples of expressions containing scalar operands are ... 

Equality Returns TRUE if operand values and lengths are exactly equal, otherwise FALSE Operands can be any synthesizable type... 

If the operands had been of different lengths, C would have been the length of ihe shortest with the index range direction of the left-hand operand. 

Operands can be different sizes. The result is the same length as the longest operand. 

Operands must usually be <32 bits but can be dif ferent sizes. The result is the same length as the left operand, rem Operands must usually be <32 bits but can be dif ferent sizes. The result is the same length as the right operand, abs Result is ffie same length as the operand. 

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