Moore state machine

In a Moore finite state machine, the output of the circuit is dependent only on the state of the machine and not on its inputs. This is described i pictorially in Figure 3-5. Since the outputs are dependent only on the j state, a good way to describe a Moore machine is to use an always state- j ment with a case statement. The case statement is used to switch between j the various states and the output logic for each state is described in the appropriate branch. The always statement can have the clock event in its] event list to indicate that it is a clocked always statement. This models the] condition of a finite state machine going from state to state synchronously j on every clock edge. The machine state itself is modeled using a reg vari-] able (a variable of reg data type). 

Here is an example of a Moore finite state machine. A reg variable] MooreState is used to model the machine state which can have either of] the four states. The event list indicates that the state transitions occur synchronously on every rising clock edge. 

A finite state machine is a quintuple Q,T,6,qo F) with Q being a finite nonempty set of states, S the finite nonempty input alphabet, 6 the transition mapping, qo a start state, and F the set of accepting states. In terms of a logic circuit, we usually let the input symbols correspond to data bits on a number of input lines and the states correspond to the values contained in the registers. In hardware applications, it is customary to introduce two derived machine concepts, known as the Moore and Mealy type machines. A (deterministic) Moore machine is described by a six-tuple (Q, S,<5,/m, r, < ), where Init is a set of initial states, T the output alphabet, and (j> Q — T the output function. In a Mealy machine, outputs are associated with the edges in the state diagram so we have Q x E —F. We will call a machine incompletely specified if the 6 function is not fully defined over its domain of states and symbols. 

The equivalence test in this case is somewhat complicated in fact, we are comparing a Mealy machine implementation (the circuit) against a Moore machine specification. In the circuit, Z is valid after the first three clock ticks and from then on after every fourth tick. In the state machine, Success might be reached after every fourth clock tick. We therefore introduce a simple modulo-four ring counter to serve as a time base ... 

A finite state machine (FSM) consists of a current state (P) and a next state (N), iq>uts (I) and outputs (O). State Machines can be classified as Mealy or Moore machines depending on how the outputs are generated. 

A Moore machine is one in which the outputs are a function of only the current state and independent of the inputs (Figure 2.5). In other words, the functionality can be expressed as. 

Systems are modelled using Moore machines. A Moore machine is a 6-tuple (transition relation, and output S O computes the current outputs from the current states. 

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