ModelSim simulator

The proposed technique to improve the throughput of RIPEMD-160 needs also to be verified. Thus the optimized design of RIPEMD-160 was developed and captured in VHDL and was fully simulated and verified using the Model Technology s ModelSim Simulator. In Table 2, the experimental results are offered. From the experimental results, it was verified that RIPEMD-160 proposed implementation was about 35% faster than the conventional implementation. 

Fault injection by simulation can be done by injecting faults at logical or electrical levels in conunercial simulators, such as ModelSim from Mentor or iSim... 

As mentioned in the previous Chapters, fault injection campaigns can be performed in different levels. The fault injection by simulation is performed by adding upsets when simulating a given system in commercial simulators, such as ModelSim from Mentor or iSim from Xilinx, or open source simulators, such as Spice. They are able to provide the best control over the experiment. This characteristic is because the simulation can be stopped at any simulation time and the internal values from anywhere inside the system can be read and stored for post-analysis. As a consequence, the amount of data is the biggest among the different levels of available fault injection campaigns types. 

In order to perform the fault injection campaign by simulation and test the fault tolerant techniques from Chap. 4, we used the fault injector proposed and described in Azambuja (2010b), which uses the commercial simulator ModelSim. The main reasons for using this fault injector were accessibility to its source code and the possibility to automate the process that could take up to weeks of computatiom... 

Timing force.do Script file to simulate mitring.v in ModelSim (timing)... 

This step is equivalent to software debugging. The HDL simulator (debugger) is provided for both functional and timing simulations. The HDL simulator is ModelSim from ModelTech,... 

At ModelSim main window type quit -sim to quit the simulation only. 

Now, we will use ModelSim to run a full timing simulation using Xilinx s Simprim and Unisim libraries. ModelSim reads the time sim.sdf file that contains the timing information from the implementation process and annotates the timing information into die time sim.vhd file. 

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