Hybrid Pixel Arrays with Data Push Architecture

1 Hybrid Pixel Arrays with Data Push Architecture 

The data push pixel and a number of related analog circuits will be submitted to MOSIS in early June, 1993 for production of a test chip by mid-July. The design of these test chips was guided both by simulation and by experience gained in previous work on the Hughes CHIP 5 array, a 32 x 64 array of time tagging pixels. The size of the pixel is 30 //m (in the 2 direction) x 135 /mi. 

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