Hole injection efficiencies heights

Figure 6. Hole injection efficiency figure of merit for substrate contacts of varying work function vs. energy step across the contact polymer interface estimated from published work function data and electrochemical redox potential data. The height of each bar reflects the variability in injection efficiency due primarily to variation in substrate surface pretreatment and for the particular case of Au, diffusion to the interface of metal atoms from underlying binder layers.

Electro-optical modulators are other examples whose efficiency is enhanced in the presence of ion-radicals. These devices are based on the sandwich-type electrode structures containing organic layers as the electron/hole-injecting layers at the interface between the electrode and the emitter layer. The presence of ion-radicals lowers the barrier height for the electron or hole injection. Anion-radicals (e.g., anion-radicals from 4,7-diphenyl-l,10-phenanthroline—Kido and Matsumoto 1998 from tetra (arylethynyl) cyclooctatetraenes—Lu et al. 2000 from bis (1-octylamino) perylene-3,4 9,10-bis (dicarboximide)s— Ahrens et al. 2006) or cation-radicals (e.g., cation-radicals from a-sexithienyl—Kurata et al. 1998 l,l-diphenyl-2-[phenyl-4-A/,A- /i(4 -methylphenyl)] ethylene— Umeda et al. 1990, 2000), all of them are electron or hole carriers. 

On the anode side, even the utilization of PEDTPSS (with a work function of ca. 5.2 eV) leaves a ca. 0.6-eV barrier for hole injection to PVK (HOMO at 5.8 eV [53]). It can thus be expected that the reduction of the barrier height for hole injection will significantly improve the power efficiency of the PVK-based devices. 

Fig. 5 shows the uniformity and smooth surface of a-7T that may contribute to the uniform injection of holes at the interface a-7T/TPD and improve the device efficiency. With the SiO layer, the device IV showed a similar current density over the range of applied voltage but showed decreased EL intensity with respect to the current density in comparison with device I (cf Fig. 2(b)). Since the SiO layer implements the height for the holes, the numbers of holes and electrons are out balanced a the HTL/ETL interface, and lowered the device efficiency. 

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