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Handle wafer

FIGURE 15.4 Representation of key steps in the layer transfer approach to 3D demonstrated by Guarini et al. and Topol et al. This approach uses a glass handle wafer and oxide-to-oxide bonding at a temperature of 300 °C (from Ref. 27, 28). [Pg.437]

As illustrated in Fig. 15.11, wafers can be bonded face-to-face, the handle of the SOI wafer can be thinned to stop on the buried oxide layer, rebonded to another handle wafer, thinned again to stop on the bonding layer, and then tested. Lu et al. have used this approach to demonstrate process compatibility on passive structures [85], Gutmann et al. have used this method to demonstrate process compatibility using active electrical structures [49], and... [Pg.448]

Consider the substrate-film system shown in Figure 6.30. The bi-layer is constrained against bending, presumably by a relatively thick handle wafer, but it is unconstrained against extension or contraction in the plane of the interface. The isotropic elastic materials of the film and the substrate have the same shear modulus p and Poisson ratio u. The common biaxial modulus is then M = 2/i(l + v)/ l — v). The elastic biaxial extensional strains in the substrate and film are denoted by Cg and Cf, respectively. The mismatch in lattice parameter is denoted by Cm. [Pg.483]

Fig. 6.30. A film-substrate bilayer system which is constrained against bending by a relatively thick handle wafer. However, the structure is free to extend or contract in its own plane. Fig. 6.30. A film-substrate bilayer system which is constrained against bending by a relatively thick handle wafer. However, the structure is free to extend or contract in its own plane.
Figure 1.12 Silicon on insulator (SOI) wafer that is used in the SOIMUMPS process. The device layer can be 10 1 pm or 25 1 (im thick. The handle wafer is 400 5 pm thick and the buried oxide layer is 1 0.05 pm thick. (Reprinted with permission from MEMSCAP Inc.) See color plate section. Figure 1.12 Silicon on insulator (SOI) wafer that is used in the SOIMUMPS process. The device layer can be 10 1 pm or 25 1 (im thick. The handle wafer is 400 5 pm thick and the buried oxide layer is 1 0.05 pm thick. (Reprinted with permission from MEMSCAP Inc.) See color plate section.
Device layer (silicon) Handle wafer (silicon) Metal (gold)... [Pg.57]


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See also in sourсe #XX -- [ Pg.15 ]




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