Flip chip issues solder bumps

Ceramic materials provide excellent CTE match between the die and package, which then reduces the risk of first-level solder bump failure in flip-chip applications. Unfortunately, this superb CTE match between the ceramic and the silicon die creates a large CTE mismatch between the ceramic package and the PWB. This CTE mismatch creates severe stress on the second level interconnects (see Fig. 58.31). This CTE mismatch, combined with DNP issues... 

Other component reliability issues related to lead-free solders include flip chips and wafer level CSPs with lead-free solder bumps and balls, where the higher soldering temperature and higher stiffness of the lead-free solder can adversely effect the reliability of the low-k dielectric layer on the die. Low k dielectric is needed for high speed applications, but is typically more fragile and prone to cracking. 

Gu, Y., Nakamura, T. Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages. In Microelectronics Reliability, Vol. 44, Issue 3 (2004), pp. 471-483. 

VIII. FLIP CHIP-RELATED ISSUES A. Characteristics of Some Lead-Free Solder Bumps... 

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