Fault tree construction representation

The fault tree is a graphic representation of the relationships between basic events and the selected top event. Table 4.24 presents the standard symbols used in fault tree construction to show these relationships. 

Numerous symbols are used in the construction of a basic fault tree. These symbols, sometimes referred to as fundamental logic symbols, provide the analyst with a pictorial representation of the event and how it interacts with other events on the tree. Figure 12.2 shows the basic symbols used during the FTA process. Once the reader has a general understanding of these symbols and their use, as described below, fault tree construction will be greatly facilitated. 

Fault tree analysis (FTA) provides a logical representation of many events and component failures that may combine to cause one critical event (e.g., pipeline explosion). It uses logic gates to show how basic events may combine to cause the critical top event. The top event would normally be a major hazard such as "pipeline SCC" as in the example shown in Fig. 12.10. The most commonly used tree symbols and gates used in the construction of fault trees are illustrated in Fig. 12.11 and briefly described here [12] ... 

The top events of a system to be investigated in FTA may also be identified through a PHA or may cortespond to a branch of an event tree or a system Boolean representation table (Wang et al. (1995)). The information produced from FMECA may be used in construction of fault trees. Detailed description of FTA and its applications can be found in various published documents such as (Andrews and Moss (2(X)2), Ang and Tang (1984), Halebsky (1989), Henley and Kumamoto (1992)). 

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