Examples Showing the Entire Test Synthesis Flow

7 Examples Showing the Entire Test Synthesis Flow 

In this section, we summarize the entire test synthesis flow by means of an example. Example 8.2 outlines the methodology to be followed for a design with bidirectional ports, three-state O/P ports, I/P and O/P ports. We illustrate the entire flow ranging from synthesis to test insertion, and JTAG synthesis followed by pad synthesis (assuming of course, that the ASIC vendor library supports that). 

Example 8.2 HDL Code for a design with bi-directional ports 

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