Edge exclusion

Fig. 5. Plot of the percentage of the maximum number of chips that can be obtained from a 200-mm wafer as a function of edge exclusion for several representative chip sizes. For small chips, the sensitivity is essentially linear, while for large chips there are plateaus in which further decreasing the edge exclusion has no impact on the percentage of possible yield.

Baker [17] derived an elegant description of the edge effect based on the mechanics of the pad and of the wafer. He argued that the peak in the edge exclusion region is proportional to where C is the slope of... 

With respect to the edge exclusion, orbital tools differ from other CMP tools because during use virtually the entire pad is in compression. In contrast, rotational tools periodically compress and then release the pad as it passes under the carrier and rotates around the tool. Very little data is publicly available regarding the fundamental properties of pads, so the significance of this difference between tool types is not well understood. 

These carriers were generally capable of providing 5-7% nonuniformity at 6- to 7-mm edge exclusion. The nonuniformity is more precisely called the within-wafer nonuniformity (WIWNU) and is defined by the standard deviation of a set of film thickness measurements on a wafer divided by the mean of that set. Smaller numbers denote better process control. Better performance was limited in part by the manner in which the carrier held the wafer during polish. 

FIGURE 13.9 Postpolishing silicon nitride ranges show greatly improved uniformity for the direct-polishing processes using HSS. This improvement is realized with smaller (3 mm) edge exclusion than was used in the other processes (8 mm). 

Edge exclusion Down to 1.5mm Typ. 6mm Relaxed Due to use of older equipment generations... 

Fig. 4. An extended run using AEP rings for 3 heads and a P ring (square symbol) for the fourth head with thermal oxide wafers at 5 mm edge exclusion. 

Fig. 6. An extended run over 3 days using AEP ring with oxide wafers at 5 mm edge exclusion. Avg. removal rate = 4053 A/min. Avg. WIWNU = 2.0%. WTWNU = 2.6%.

Fig. 8. An extended run using AEP ring with W wafers at 5 mm edge exclusion.

All of the cleans to be discussed were evaluated for metal ion contamination by using the SIMS procedure previously described by Phillips, et al (J ). Particle contamination was determined using a Tencor Surfscan set at maximum sensitivity (lym) with an edge exclusion setting of 7- All of the samples were prepared and cleaned as previously described (19) unless stated otherwise. 

Extreme deposit thickness uniformity requirements ([Pg.26]

Figure 2 Photoluminescence mapping of an InGaN MQW structure on 4 inch sapphire. No edge exclusion was applied.

Sparks, C., Beebe, M. (2004) Trace metal contamination analysis of the bevel and edge exclusion area on starting silicon. In High Purity Silicon VIII, edited by Claeys, C., Watanabe, M., Falster, R., Stallhofer, P. Pennington, NJ The Electrochemical Society, pp. 329-333. 

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