Duty Cycle Gate Drive Circuit

UC1846 50% Duty Cycle Gate Drive Circuit 

This circuit was used in Chapter 10 as part of a high-voltage and high-current doubler. This circuit can provide a fixed-frequency, fixed 50% duty cycle square wave capable of driving the gate of a power MOSFET. 

The circuit is shown in Fig. 9.1. It is powered by a 15 V supply connected to Vin and Vc (pins 15 and 13). A bypass capacitor is applied across the power of the IC to help minimize noise effects. The frequency of the output is set by resistor R5 and capacitor C3. 

The frequency is fixed at 50 kHz, with a 50% duty cycle. The noninverting terminal of the error amplifier is tied to the reference voltage (5.1V) and the inverting terminal is tied to ground, so that the oscillator controls the pulse termination. The output signal appears at Aout (pin 11). 

Our equivalent SPICE model of this circuit is shown in Fig. 9.2. A 100 M 2 resistor (R4) has been added from the inverting terminal of the current sense pin to ground in order to help convergence and prevent singular matrix errors. 

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Figure 9.1 Schematic of UC1846 fixed duty cycle gate drive circuit.

Circuits where isolated gate drives operate at nearly full duty cycle or nearly zero duty cycle can be difficult to design. The transformer that provides isolation can easily saturate at full duty cycles. The circuit featured here uses a unique idea in order to circumvent this difficulty. 

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