Design trajectory

Overview of the HlFl design trajectory for regular processor 

Since we focus here on a regular design, the structure node has special constructs for exploring regularity. This is achieved by arranging the network elements in a number of sets of indexed elements [11, 20]. 

Definition 4.1 Let L be an n x m integer matrix and O be a vector in where Z denotes the set of integral numbers, A lattice l(LjO) is a set of regularly spaced integral points / G characterized by the relation  

Definition 4.2 Let I be a lattice, A domain, D, is a set of integral points I of the lattice I enclosed by a polytope. Let A be an r x n integer matrix and C be a constant vector in Then a domain is characterized by  

5 and M = 4. The dotted lines are the half planes, which are derived from the bounds of the FOR-loop statements. 

---

The goal of the work on architecture synthesis within the Ascis and Nana projects has been to contribute design methodologies and synthesis techniques which address the design trajectory from real behavior down to the RT-level structural specification of the system. Our view of this synthesis process is illustrated in figure 1. 

Figure 1 Architecture synthesis as viewed within the Ascis and Nana projects. The input from the user is converted to a formal system model which can also be written out in a readable specification format. Different design trajectories must be followed, depending on the characteristics of the application. The figure only shows the two main branches we have addressed. The final high-level performance-driven controller synthesis is similar for both branches. In the next design stages, which have not been addressed by the projects, the detailed synthesis of the data-paths and controllers on the RT and logical levels still has to take place. This is then followed by the physical design stage.

Hence, we have felt the need for several extensions to the design trajectory ... 

P. Dewilde and E. Deprettere. Architectural synthesis of large, nearly regular algorithms design trajectory and environment. Annales des telecommunications, 46, number 1-2, pages 48-59, Jan-Feb 1991. 

We first briefly review the well-known basic synthesis method. Then we focus upon extensions of this original method, such as more efficient scheduling and bounded broadcast facilities, and also the embedding in a more complete system design trajectory, which also requires, for instance, extraction of the uniform DG and partitioning of the solution on a fixed size array. Where appropriate, we will also refer to the methods described in the other chapters. 

Typically, an algorithm will be specified in the form of a nested loop program (NLP) [3]. It is useful to include the specification of a nested loop program as an integral part of the design trajectory, mainly because it can be specified in an easily comprehensible syntax and because such a program often can be found in a library. 

Unfortunately, an NLP does not explicitly show the parallelism of the computations. Therefore, the first step in the design trajectory is to convert the NLP into a dependence graph (see chapter 2) [4]. The resulting DG will have a node for each instance of the calculation of a function, e.g., Floyd in the example below. Its edges will represent the passing of arguments between those functional nodes and hence implement function calls. We will discuss the conversion step in more detail in section 5. Similar functionality is provided in the approach of chapter 5 but for a partly different target domain. 

The goal of the hardware synthesis work within these projects has been to contribute design methodologies and synthesis techniques which address the design trajectory from real behavior down to the RT-level structural specification of the system. In order to provide complete support for this synthesis trajectory, many design problems must be tackled. We do not claim to cover the complete path, but we do believe we have contributed to the solution of a number of the most crucial problems in the domains of specification and synthesis. We therefore expect this book to be of interest in academia not for detailed descriptions of the research results—these have been published elsewhere—but for the overview of the field and a view on the many important but less widely known issues which must be addressed to arrive at industrially relevant results. 

Completeness. The complete design trajectory should be covered, from a verifyable, bit-true algorithmic specification up to a register-transfer (RT) level description of the architecture. This includes well known synthesis tasks like allocation and scheduling, but also novel tasks like the optimisation of background memory (RAM, FIFOs), or the accommodation of the bit-level specifications in the final architecture. 

Interactivity. Last but not least, the designer should be able to interact with the compiler at all levels of the design trajectory e.g. to overrule compiler decisions or to apply additional local optimisations to the critical parts of the design. 

---