Optimization DATAFLOW

The controlflow/dataflow graphs are rearranged and optimized. Using a percolation algorithm, the vertices are scheduled into specific states, subject to data dependencies, resource limits, and other constraints. 

Speed optimization is usually applied after area optimization has taken place. Speed optimization will improve the performance but only to a certain extent. If after speed optimization the circuit still does not meet the design specification, then the designer must go back and restructure the VHDL. Often this approach involves replacing a behavioural specification with a dataflow or structural one. A good example would be replacing a behavioural description of an add operation by a structural equivalent that implemented a fast carry-propagate mechanism. 

Logic synthesis and optimization results Synthesis of the dataflow architectures... 

The aidiitectures DATAFLOW , DATAFLOW2 and DATAFLOW4 produced an identical circuit after optimization. This is shown in Figure 4.18. The logic of the circuit has been minimized to the form shown in equation 4.4. 

Table 4.4 Logic synthesis and optimization statistics for the dataflow style architecture...

Figure 4.18 DATAFLOWI, DATAFLOW and DATAFLOW4 optimized circuit...

Table 5.1 Logic synthesis and optimization statistics for four synchronous dataflow-style architectures with and without external initialization signals. Compares If and Wait versions...

Table 6.2 Logic s)nithesis and optimization statistics for the ripple carry adder architectures and the signed dataflow structure. Timing constraints were met in each case. No final area constraint was applied...

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