Compiling Hierarchical Designs

In most cases, hierarchical designs are not compiled top down or bottom up. It is usually a combination of the two. This is most common when a chip uses existing sub modules available either in HDL netlist form or in schematics. Often, the design is a combination of pre-existing design blocks and newly designed blocks. In such cases, from the top level one has a fair idea of the constraints. In such a scenario, your approach should be as follows  

Read in all the sub blocks of your design, and finally your top level. 

Characterize and compile each sub-block individually. In other words, you have two sub-designs s1 and s2 (instance names are u1 and u2 respectively) contained in top. The dc shell script will be as follows  

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ISIS databases are hierarchical, so CHIRBASE was designed to incorporate about 60 data fields on several levels of detail (the main fields are listed in Table 4-2). The first level contains the molecular structure of the sample combined to the molecular structure of the CSP, producing a unique location or entry for a specific sample-CSP couple. Consequently, in the current version of CHIRBASE, which contains 40 000 entries, one entry corresponds to the separation of one sample on one CSP and contains in different sublevels a compilation of all the references and the various analytical conditions available for this separation. 

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