CdSe Thin Film Transistor Switch Matrix Address

An example image displayed on the MIM diode addressed matrix liquid crystal display panel is shown in Fig. 6 [27], The actual display area is 100x96 mm. There are 240 gate and 250 data electrodes which provide a resolution of 25 lines cm . The contrast ratio obtainable is very high. 

2 CdSe Thin Film Transistor Switch Matrix Address [37-56] 

The gate and data electrode buses are located on a glass substrate and separated by a thin isolating layer inserted at their intersection. The rectangular shaped transparent pixel electrode is surrounded by the gate and data electrode buses. 

A tiny TFT is placed at each intersection of the gate and data electrode buses. Its drain and source electrodes are connected to the data electrode bus and the pixel electrode, respectively. The TFT gate electrode is connected to the gate electrode bus. Thus, each TFT is used to control the optical characteristics of the associated liquid crystal pixel of the matrix. 

A glass substrate, which has a transparent common electrode on its inner surface, is placed facing this matrix pixel substrate as shown in Fig. 7 (b). A liquid crystal molecular alignment layer is provided on the 

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Figure 9. An image displayed with the CdSe-thin film transistor switch matrix addressed liquid crystal display panel. (Courtesy of Stuttgart University).

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