Binary decoder

Using the characteristics of the circuit shown in Fig. 7.1, we can add AND gates and create a binary decoder circuit. The binary decoder circuit looks at two input signals and determines whether the signal corresponds to a 0, 1, 2, or 3. The truth table for the binary decoder is shown in Table 7.1. 

The Micro-Cap simulator was exact enough to show the slight overlap of the decoder after code 1 and code 3. This is a result of the 

The IsSpice and PSpice simulation results are shown in Figs. 7.11 and 7.12. The simulation results from the IsSpice and PSpice are in the same format as the results from the breadboard and the Micro-Cap simulator. 

50uS 6Qu 7QuS BOuS 90US 10 Dus 11 Dus 120uS 13 Dus 14DuS 

Advantages Accurate, very low propagation delay Disadvantages Can be realized with fewer parts 

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A binary decoder, a binary adder, and a stack memory can be built. 

Figure 7.7 Breadboard results of the binary decoder circuit (0 and 1).

Synthesized netlist of a 2-bit binary decoder is shown //in Figure 3-21. 

These functions are easily implementable. Encoding is as simple as a XOR tree or equivalent circuitry or algorithm per parity bit. s is calculated in the same way. Correction can be implemented using a 5-to-32 binary decoder and some logic gates. It is important to note that no correction is performed in case of error detection . 

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