Basic principles of combinational design

Pure combinational logic primarily implements data-driven elements of a circuit and any simple associated controlling logic. These elements can be anything from 2-bit multiplexers to 16 x 16 bit multipliers. The architectural style adopted will be determined by, among others, the following factors. 

Although it is important to consider all these issues, for most fully data-driven circuit elements the dataflow style is often the most appropriate. These elements are best joined together through a structural higher level in which common components can be easily replicated. 

The examples in flus chapter will illustrate how all architectural styles can also be applied to a straightforward design. 

VHDL defines logical operators for the basic types of BIT and BOOLEAN or any one-dimensional array of either type, such as BIT VECTOR. The result generated by each operator is of the same type and has the same length as the operands supplied. Hence, the operands must be identical in type and length to allow each matching element to be compared. The synthesizer should detect any errors of this t)rpe, but they may go undetected until run time when simulating the description. The operators are listed in Table 4.1. 

The Not operator belongs to a class of operators that have the highest precedence. The rest of the logical operators have the equal lowest precedence of all operators. A summary of operator precedence is given in Appendix A. 

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