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Back-Gated Devices

Another example of an Si-based pH sensing device is an electrolyte-insulator-semiconductor (EIS) structure. In a typical EIS sensor, a voltage applied to the semiconductor back gate (Vgate) attracts ions in the electrolyte to the oxide surface. The... [Pg.297]

Due to the significant distribution of diameter and chirality of the nanotubes in the raw material, it is important to characterise SWCNTs incorporated into an FET configuration individually. In this section, we discuss the important device parameters of CNT-FETs fabricated in the two gating configurations. Following this, we introduce a novel device characterisation technique based upon local photocurrent detection, which enables the estimation of electronic band profiles of back-gated CNT-FETs. [Pg.585]

Fig. 3.8 Device configurations of back-gated oriented (a) and random CNT-TFTs (b) with Au source/drain electrodes, c AFM topographical image of a CNT-TFT with uniaxially ordered micropatterned CNT array, d AFM topographical image of a CNT-TFT with randomly oriented CNT surface film. Reproduced with permission from [85]. Copy right 2006 American Chemical Society... Fig. 3.8 Device configurations of back-gated oriented (a) and random CNT-TFTs (b) with Au source/drain electrodes, c AFM topographical image of a CNT-TFT with uniaxially ordered micropatterned CNT array, d AFM topographical image of a CNT-TFT with randomly oriented CNT surface film. Reproduced with permission from [85]. Copy right 2006 American Chemical Society...
Due to the inability to deposit eleetrochemically stable gate-insulating materials for GaAs, another approach was developed based on amorphous silicon (a-Si), prepared as a thin layer for LAPS devices on transparent glass substrates [40]. The diffusion length in this material was reported to be as small as 120 nm [41] and a resolution down to 1 gm has been demonstrated, which was mainly limited by the optical set-up. The electrochemical properties of the a-Si-based structures were investigated later with a LAPS device thus, the above results for SPIM were transferred back and proved for the LAPS, too [42,43]. [Pg.99]

Figure 10 illustrates the short-term dc stability of the devices (Mackenzie et al, 1983). The output characteristics of one FET are shown for 10 successive scanning cycles of VG from —10 V to +45 V and back. The gate voltage was scanned in both directions at a rate of about 0.5 V sec-1. The traces show remarkably little drift or hysteresis in fact, the maximum variation in VG is approximately 0.4 V for a given value of source-drain current. [Pg.99]


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Back-gating

Gate device

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