ASIC Vendor Issues

The test strategy used for a design is almost completely dependent on the requirements of the ASIC vendor. In other words, the requirements of the ASIC vendor must be taken into consideration prior to deciding on the test synthesis strategy. Listed below are some of the critical issues which involve the ASIC vendor. 

What scan style does the ASIC vendor support  

ASIC vendors usually support only some scan styles and not all the available scan styles. Most ASIC vendors support the multiplexed scan flip-flop style. 

How many clocks are supported by the tester when in test mode  

Is there a limit on the number of waveforms supported by the tester  

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Scan technique is the most widely used Design For Testability(DFT) technique, and more importantly, is supported by most test synthesis tools. Iliis technique involves replacing the sequential non-scan cells by scan cells of the desired scan style. This transformation enables the sequential scan cells to be connected as a shift register in the scan mode. Further, for ATPG each of these scan cells behave as a pseudo primaiy input as well as a pseudo primaiy output. In this section, we discuss four basic issues related to Test Synthesis using TC, namely. Scan methodology. Scan Style, Scan Insertion and ASIC Vendor issues. 

To transfer a design from DC to another EDA vendor tool via EDIF schematics, all the symbols used in the schematic must be from the ASIC vendor symbol library and not from the generic.sldb, the Synopsys generic symbol library. It is important to remember that a symbol library in system A is not the same as a symbol library in system B even if the cell names and interfaces match. Therefore, when dealing with schematic problems, the important issues to know are as follows ... 

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