Application domain and target architecture

The application domain and ASIC emulator architecture strongly influence the overall synthesis script as well as the actual algorithms for solving single synthesis tasks. In order to achieve efficient solutions, our whole approach has been tuned toward real-time system applications as they are found in mechatronic systems. To support the understanding of the implemented approach/algorithms, this section will describe the intended application domain and ASIC emulator architecture in more detail. 

This synthesis approach is tuned toward real-time applications appearing in mechatronic systems, such as an adaptive shock absorber, a combustion engine controller, intelligent tire friction control, volume stream measurement, etc. A large number of microelectronic subcomponent designs have been studied [8]. As a result, it was found that the designs typically share the following common characteristics  

The data/control-flow graphs are large and complex. Moreover, the applications require clock frequencies of 10 20 MHz, whereas the intermediate data throughput and sample frequencies remain far below 1 MHz. As a result of these factors, the hardware-sharing factor (HSF) is much larger than 1, resulting in highly multiplexed architectures. 

Some applications require floating-point arithmetic (which is not supported by the emulator board and module library). 

There are only one- and two-dimensional data streams (vectors and matrices) of complex data types (large integer, fix). Typical vector sizes are 10-500 elements. Arrays with two dimensions have less than 10 entries in 

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