An imaginary 2.-D system see colour plate

Intuitively, many advantages can be expected through the adoption of 2.5-D integration scheme. A few of these are discussed below. 

CAD tools to find a more efficient packing of circuits according to their inherent topology. Thus, a systematic reduction in the on-chip wire length can be expected, which can be translated into speed gain, power saving, and many other advantages. 

Meanwhile, validating a die in a 2.5-D system is quite similar to verifying an embedded IP core from the testing point of view. Thus, recently developed testing methods for core-based designs1441 provide another set of testing solutions for the 2.5-D system as listed below  

The essence of the above techniques is to enable separate access to each embedded IP core in a system while trying to reuse existing functionality as much as possible. Accordingly, these testing solutions can be straightforwardly adapted to the purpose of testing 2.5-D systems. 

Process Standard CMOS, RF-CMOS, SiGe, Embedded memory 

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