An Analytical Performance Model

The most commonly used metric for CPU performance is Instruction per Cycle (IPC). However, its reciprocal, Cycle per Instruction (CPI), is a more appropriate metric for an analytical analysis since it could be formulated as a sum of factors representing the impact of various microarchitecture features. The essential idea of the analytical modeling is illustrated in Fig. 3.13. 

On an ideal microprocessor with an infinite Level 1 (LI) cache, every memory access hits. The resultant CPI value, CPIjdeai, is completely determined by the inherent parallelism of the application as well as the limit of computational resources. Certainly there is no such an ideal microprocessor in reality. As a matter of fact, LI cache has to be configured with a relatively small capacity so 

As long as a LI cache miss happens, CPU will then query the L2 cache as illustrated in Fig. 3.13. Every access to L2 cache, no matter a hit or a miss, has to incur a latency time, T2, which is the sum of such factors as SRAM pre-charge delay, word line decoding, bus delay, and so on. The latency incurs a penalty to the CPI metric as  

Besides the memory word required by the current instruction, a LI cache miss 

All these data traffics are through a dedicated bus between LI and L2 caches. Accordingly, the bus has to be modeled as a queue. The service time S2 is constant since every time a fix-sized cache line is transferred  

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