Allocation module assignment

High-level synthesis has been an active area of research for over 20 years. The main problems involved, such as scheduling, allocation and module assignment, have been well characterized and solved. Nevertheless, high-level synthesis systems are not yet common on the marketplace. We see four principal reasons for this. 

Allocation, which assigns each operation to a piece of hardware. Allocation involves both the selection of the type and quantity of hardware modules from a library (often called module assignment) and the mapping of each operation to the selected hardware. Allocation is sometimes called data path synthesis or data path allocation. 

Uses a set of small transformations, including multiplexor reduction, allocation of assignment operations, and data path partitioning, plus several translation steps, which perform the module binding. 

In HIS, module assignment is performed during constraint generation, prior to scheduling (and allocation). In this way, all further synthesis steps can be performed with given modules, regardless of the library used. 

One line of the helium purification facility is directly assigned to each of the two HTR-modules. A third purification line is available in the case of fault-incurred failure, maintenance work and regeneration operation of the directly allocated line. The through-put of a purification line amounts to 5% of the primary circuit inventory per hour. 

Control Step Scheduling and Data Path Allocation. Control step scheduling (CSTEP) and data path allocation (EMUCS) are the last of the major phases of the Workbench shown in Figure 9-1. The control step sequencing and data path allocation tools synthesize modules to perform the operations and transfer and store the values it finds in the VT. They assign all the operators in the VT to control steps and bind individual values and operators in the VT to specific modules in the synthesized structure. Only the EMUCS data path allocation tool has been integrated into the CORAL system. 

The basic idea behind this work is the following as operations are scheduled and functional modules are allocated, we decide their shape and position on the floorplan concurrently. The approach taken is to schedule the operations along the critical path first and assign (and place, if the assigned operator is newly allocated) operators as close as possible to their predecessor(s) according to their data dependencies without violating user specified constraints. Then, the off-critical path operations are scheduled and assigned to operators. 

As depicted in Figure 1-3, there were multiple levels of documents increasing in detail. Level 2 documents address five different categories as depicted below. The requirement allocation process that was planned for the JIMO project would have assigned requiremer ts from each tier of documents, as well as interface requirements and other derived requirements, to the next lower level elements. In this way, requirements would have been assigned to the various modules and then to their constituent segments, sub-systems, etc. A tabular depiction of the project hierarchy, and description of the reactor module segments, follows. 

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