Transputer networks

Wedig, Burkhardt, and von Schnering reported the use of the native programming language Occam for Transputer network applications in computa-... 

Special emphasis has also been given by Bhusari, Bhate, and PaT jq the implementation of the four-index transformation on a Transputer network, as part of a general program of parallel ab initio algorithm development. Results were presented on a four-node machine. 

Ed., Proceedings of the Third Conference of the North American Transputer Users Group, April 26-27, 1990, Sunnyvale, CA, lOS Press, Amsterdam, 1990, pp. 63-74. The Fast Multipole Algorithm on Transputer Networks. 

Brint, A.T. and Willett, P. (1987b). Identifying 3-D Maximal Common Substructures Using Transputer Networks. J.Mol.Graphics, 5,200-207. 

A. T. Brint and P. Willea,/. Mol. Graphics, 5,200 (1987). Identifying3D Maximal Common Substructures Using Transputer Networks. 

Transputers. At higher levels of coimectedness there is a wide variety of parallel computers. A great many parallel computers have been built using INMOS Transputer chips. Individual Transputer chips mn at 2 MELOPS or greater. Transputer chips have four communication channels, so the chips can readily be intercoimected into a two-dimensional mesh network or into any other interconnection scheme where individual nodes are four-coimected. Most Transputer systems have been built as additions to existing host computers and are SIMD type. Each Transputer has a relatively small local memory as well as access to the host s memory through the interconnection network. Not surprisingly, problems that best utilize local memory tend to achieve better performance than those that make more frequent accesses to host memory. Systems that access fast local memory and slower shared memory are often referred to as NUMA, nonuniform memory access, architecture. 

As part of their efforts to employ parallel computers for molecular dynamics simulations, Schulten and co-workers generated a series of MD benchmarks based on their own program on a wide range of machines, including an Apple Macintosh II, a Silicon Graphics 320 VGX, a 32K-processor Conneaion Machine CM-200, a 60-node INMOS Transputer system, and a network of Sun workstations (using Linda).2 8 j e benchmarks demonstrated that the program runs very efficiently on many platforms (e.g., at sevenfold Cray 2 processor speed on the CM-200 and at Cray 2 processor speed on the Transputer system). 

Consider the above example of 100 pieces of information, but instead of being processed serially, the information is carried over a network of ten electronic tracks. Now the time taken to move this information is only 1 msec viz., the system is ten times faster than the serial one. However, simply providing ten new tracks is not an answer in itself. Each track must be provided with its own microprocessor to deal with the information, and the processors must be able to communicate with each other so the information flows in an orderly fashion. (It is no use having two different train tracks if each train arrives at the same platform at exactly the same time ) Thus, the transputer is a microprocessor that has its own memory bank and input and output lines enabling... 

Second, neural networks that may store knowledge implicitly and find appropriate answers after presentation of training patterns or structures (cf Section 8.2) are exploited. Neural networks are built at present by using conventional programming languages. In the future, however, parallel operating computers or transputers will be applied. 

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