Timing-Driven Placement with Buffering

Consider the problem of maximizing the minimum slack of a given subcircuit G with some movable gates and some fixed gates, or ports. Let the set of nets in the subcircuit be N = o, i, , Let the set of all gates in the subcircuit (movable and fixed) be G = go, Let the set of movable gates in the subcircuit 

The calculation of Required Arrival Time (RAT) and Actual Arrival Time (AAT) of a gate for combinational circuits shown in Fig. 3.7 are computed as follows. The RAT of a combinational gate g 

3 Buffer Insertion During Timing-Driven Placement 

Given a clocked latch r, we assume for simplicity that the RAT (Rr) and AAT (Ar) are fixed and come from the timer. Unclocked latches are treated similarly to the combinational gates above. 

The slack of a timing arc rip, connecting two gates (combinational or sequential, movable or fixed) p and q is 

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Luo T, Papa DA, Li Z, Sze CN, Alpert CJ, Pan DZ (2008) Pyramids an efficient computational geometry-based approach for timing-driven placement. In ICCAD, pp 204-211 Shi W, Li Z, Alpert CJ (2004) Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. In ASP-DAC, pp 609-614... 

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