Time Measurement by Fast TAC ADC Principle

Because of its superior time resolution the conventional TAC-ADC technique used in the classie TCSPC setups is still used in advaneed TCSPC devices. However, the conventional TAC-ADC teehnique has been upgraded by a modified ADC principle that cancels the nonuniformity of the ADC eharacteristics. With the new ADC technique, ADC ehips with moderate aeeuraey but extremely high speed can be used. Together with a speed-optimised TAC eireuitry, the new ADC technique achieves exceptionally high conversion rates. 

To obtain a high differential linearity of a TAC two points are essential a fully differential design, minimising erosstalk between the start and stop signals, and switehes with low switehing transients. A practical implementation is shown in Fig. 4.5. 

In practice a TAC circuit contains additional circuitry that generates a start pulse for a subsequent ADC, resets FFl and FF2 after the ADC has sampled the 

The TAC module of a Becker Hiekl SPC-830 TCSPC deviee is shown in Fig. 4.6. The module is built in chip-and-wire hybrid technique. Most of the semi-eonduetor ehips are inserted as bare diee eonnected to the signal lines on the substrate by bond wires. 

The ADC of a TCSPC system has to work with an extremely high accuracy. It has to resolve the TAC signal into several thousand time channels, and the width of the particular channels must be equal within 1% or better. ADC chips are usually specified by a nonmissing code accuracy which defines the number of bits for which the ADC characteristics is still monotonous. 12-bit conversion with a channel uniformity of 1% requires a nonmissing code accuracy of 19 bits. Although ADCs with such a high accuracy exist, they are far too slow for TCSPC applications. Therefore, in the early TCSPC systems, the ADC was the bottleneck both in terms of speed and channel uniformity [383]. 

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