The RUMBLE Timing Model

We now introduce the timing model critical to RUMBLE S success. 

3 Buffer Insertion During Timing-Driven Placement 

Where L is the length of a 2-pin buffered net, Rb and Cb are the intrinsic resistance and input capacitance of buffers and gates while R and C are unit wire resistance and capacitance respectively. 

The model is further simplified by assuming continuous gate sizes and placement sites. Then optimal buffering solutions minimize the delay function as follows. 

Which leads to this relation on the optimal buffering solution. 

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