Synthesis, Optimization and Compile

Example 1.11 shows a simple dc shell script to read in a design, compile, and write out a netlist of the design in VHDL. The file constraints.scr must contain timing and area constraints. Optimization constraints are discussed in greater detail in Chapter 4. For man pages on any of the DC commands, use the help command at the dc.shell prompt as shown below  

DC maintains a synopsys cache directory, where DW components which are inferred (or instantiated) from technology library cells are saved (or written out). This prevents the need to re-build these components, each time a compile step is executed. Reading and writing to this location is controlled by the cache read and cache write variables. Also, if the cache read info and cache writeJnfo variable are set to true, DC issues a message each time the cache is written to, or read from. 

In this section, we describe a few classic scenarios faced by designers when using DC. This section is especially useful for designers new to DC. 

These warnings could be because of one of the following reasons  

The search path variable is incorrectly specified. Check the search path variable to verify that the UNIX paths to the target and link library have been specified correctly. At the prompt use the following command. 

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