Synopsys FPGA Compiler Flow

This section describes the complete design flow to be followed when synthesizing a VHDL A/erilog description to a Xilinx 4000 device using the FPGA Compiler. At each stage the relevant dc.shell commands are provided. The. synopsys dc.setup 

Read in your HDL code using the read command with the appropriate options. The read command performs syntax checking and basic code optimization such as, constant propagation and dead-code elimination before creating a network of logic equations and registers. 

Specify timing and other optimization constraints on the design as shown in example dc shell script below. 

Use FPGA Compiler to map the design to CLBs and lOBs. The compile command produces a netlist of CLB, lOB, TBUF cells, and a limited number of special cells (latches and adder/subtracter cells from the Xilinx DesignWare library) from the FPGA library. 

Write out a Synopsys. db file netlist of CLBs and lOBs. write -hler -o pre xnf.db 

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